The ARM (Advanced RISC Machine) has launched several processors that have different features as well as the different cores for a wide variety of applications. The first ARM architecture design has 26-bit processors, but now it reached 64-bit processors. The general expansion of ARM products cannot be categorized into some particular information. But ARM products can be understood based on its architecture. The standard ARM series processors available in the market are starting from ARM7 to ARM11. These processors have several features like cache, Data Tightly Coupled memory, MPU, MMU, etc. Some of the widely known ARM processor series are ARM926EJ-S, ARM7TDMI, and ARM11 MPCore. This article is particularly intended for ARM7 based LPC2148 microcontroller architecture overview which will give you brief information about the microcontroller architecture.
The ARM7 is a 32-bit general-purpose microprocessor, and it offers some of the features like little power utilization, and high performance. The architecture of an ARM is depended on the principles of RISC. The associated decode mechanism, as well as the RISC- instructions set are much easy when we compare with microprogrammed CISC-Complex Instruction Set Computers.
The Pipeline method is used for processing all the blocks in architecture. In general, a single instruction set is being performed, then its descendant is being translated, & a 3rd-instruction is being obtained from the memory.
An exclusive architectural plan of ARM7 is called as Thumb, and it is perfectly suitable for high volume applications where the compactness of code is a matter The ARM7 also uses an exclusive architecture namely Thumb. It makes it perfectly suitable for different applications by memory limitations where the density of code is a matter.
Every peripheral device consists of a single interrupt line allied to the VIC (vector interrupt controller), although it can have various interrupt flags inside. Individual interrupt flags can also signify one or more interrupt resources.
The microcontroller LPC2141/42/44/46/48 includes a flash memory like 32-kilobytes, kilobytes, 128-kilobytes, 256-kilobytes respectively. This flash memory can be used for both data storage as well as code. The flash memory programming can be done in the system through the serial port.
The program application may also erase while the application of the program is running, permitting flexibility of data storage field firmware improvements, etc. Because of the selection of an architectural solution for an on-chip bootloader, the available memory for the microcontrollers LPC2141/42/44/46/48 is 32-kilobytes, kilobytes, 128-kilobytes, 256-kilobytes, & 500-kilobytes. The flash memory of these microcontrollers’ offers 1, 00,000 erase per cycles and data preservation for many years.
This block permits chosen pins of the ARM7 based LPC2148 microcontroller for having several functions. The multiplexers can be controlled by the configuration registers for allowing the link between the pin as well as on-chip peripherals.
Peripherals must be coupled with the suitable pins previous to being triggered, and previous to any connected interrupts being permitted. The microcontroller functionality can be defined by the pin control module by its pin selection of registers in a given hardware environment.
After rearranging all pins of ports (port 0 & port 1) are arranged as i/p by the given exceptions. If debug is allowed
If debug is allowed, the pins of the JTAG will guess the functionality of JTAG. If a trace is allowed, then the Trace pins will guess the functionality of trace. The pins connected to the I2C0 and I2C1 pins are open drain.
GPIO registers control the device pins which are not linked to a particular peripheral function. The device pins can be arranged as i/p[s or o/ps. Individual registers allow for clearing any number of o/p’s concurrently. The output register value can be read back, & the present condition of the port pins. These microcontrollers begin an accelerated function over LPC200 devices.
General-purpose input/output registers are moved to the processor bus used for the best probable I/O time.
The microcontrollers like LPC2141 or 42 include two ADC converters, and these are only 10-bit have one & the LPC2144/46/48 have two ADC’s, and these are only 10-bit straight approximation ADC’s. Although ADC0 includes 6-channels and ADC1 has 8-channels. Thus, the number of accessible ADC i/ps for LPC2141 or 42 is 6 & 14 for LPC2141 or 42.
The DAC allows these microcontrollers to produce a changeable analog o/p, and VREF is the utmost output of a digital to an analog voltage.
The universal serial bus consists of 4-wires, and that gives the support for communication between a number of peripherals and hosts. This controller allows the bandwidth of USB for connecting devices using a protocol based on the token.
The bus supports unplugging hot plugging and dynamic collection of the devices. Every communication is started through the host-controller. These microcontrollers are designed with a universal serial bus apparatus controller that allows 12 Mbit/sec data replaced by a host controller of USB.
These microcontrollers include two UARTs for standard transmit & get data-lines. Contrasted to earlier microcontrollers (LPC2000), UARTs in microcontrollers LPC2141/ LPC2142/ LPC2144/ LPC2146/ LPC2148 initiate a partial baud rate generator used for both UARTs, allowing these types of microcontrollers for achieving typical baud rates like 115200 by every crystal frequency over 2 MHz. Additionally, the control functions like CTS/RTS are completely executed in hardware.
Each microcontroller from LPC2141/ LPC2142/ LPC2144/ LPC2146/ LPC2148 includes two I2C bus controllers, and this is bidirectional. The inter-IC control can be done with the help of two wires namely an SCL and SDA. Here the SDA & SCL are serial clock line and the serial data line
Every apparatus is identified by an individual address. Here, transmitters and receivers can work in two modes like master mode/slave mode. This is a multi-master bus, and it can be managed by one or more bus masters linked to it. These microcontrollers support up to-400 kbit/s bit rates.
These microcontrollers include a single SPI controller and intended to handle numerous masters & slaves associated with a specified bus.
Simply a master & a slave can converse over the interface throughout specified data transmission. During this, the master constantly transmits a byte-of-data toward the slave, as well as the slave constantly transmits data toward the master.
These microcontrollers contain single SSP, and this controller is capable of process on an SPI, Microwire bus or 4-wire SSI. It can communicate with the bus of several masters as well as slaves
But, simply a particular master, as well as slave, can converse on the bus throughout a specified data transmit. This microcontroller supports full-duplex transfers, by 4-16 bits data frames used for the flow of data from the master- the slave as well as from the slave-the master.
Timers and counters are designed for counting the PCLK (peripheral clock) cycles & optionally produce interrupts based on 4-match registers.
And it comprises four capture i/ps to catch the value of a timer when an i/p signals change. Several pins could be chosen to execute a particular capture. These microcontrollers can calculate exterior events on the inputs of capture if the least exterior pulse is equivalent. In this arrangement, idle capture lines can be chosen as usual timer capture i/ps.
The watchdog timer is used for resetting the microcontroller in a reasonable sum of time. When it is allowed then the timer will produce a reset of a system if the consumer program does not succeed to reload the timer in a fixed sum of time.
The RTC is intended for providing counters to calculate the time when the idle or normal operating method is chosen. The RTC uses a small amount of power and designed for appropriate battery power-driven arrangements where the central processing unit is not functioning constantly
These microcontrollers support two condensed power modes such as power-down mode and idle mode. In Idle mode, instructions execution is balanced until an interrupt or RST occurs. The functions of peripheral maintain operation throughout idle mode & can produce interrupts to cause the CPU to restart finishing. Idle mode removes the power utilized by the CPU, controllers, memory systems, and inner buses.
In power down mode, the oscillator is deactivated and the IC gets no inner clocks. The peripheral registers, processor condition with registers, inner SRAM values are conserved during Power-down mode & the chip logic levels output pins stay fixed.
This mode can be finished and the common process restarted by specific interrupts that are capable to work without clocks. Because the chip operation is balanced, Power-down mode decreases chip power utilization to almost zero.
The PWMs are based on the normal timer-block & also come into all the features, though simply the pulse width modulator function is fixed out on the microcontrollers like LPC2141/42/44/46/48.
The timer is intended to calculate PCLK (peripheral clock) cycles & optionally produce interrupts when particular timer values arise based on 7-match registers, and PWM function also depends on match register events.
The capability of individually control increasing & decreasing boundary positions allows the pulse width modulation to be utilized for several applications. For example, the typical motor control with multi-phase uses 3-non-overlapping outputs of PWM by separate control of every pulse widths as well as positions.
The VPB divider resolves the association between the CCLK (processor clock) and the PCLK (clock used by peripheral devices). This divider is used for two purposes. The first use is to supply peripherals by the preferred PCLK using VPB bus so that they can work at the selected speed of the ARM processor. In order to accomplish this, this bus speed can be reduced the clock rate of the processor from 1⁄ 2 -1⁄ 4.
Because this bus must work accurately at power-up, and the default state at RST (reset) is for the bus to work at 1⁄ 4th of the processor clock rate. The second use of this is to permit power savings whenever an application doesn’t need any peripherals to work at the complete processor rate. Since the VPB-divider is associated with the output of PLL, this remains active throughout an idle mode.
The microcontroller (LPC2141/42/44/46/48) holds emulation & debugging through serial port-JTAG.A trace-port permit tracing the execution of the program. Trace functions & debugging concepts are multiplexed with port1 and GPIOs.
The code security feature of these microcontrollers LPC2141/42/44/46/48 permits a function to control whether it can be protected or debugged from inspection.
Thus, this is all about ARM7 based LPC2148 microcontroller architecture. From the above article, finally, we can conclude that ARM is an architecture used in numerous processors as well as microcontrollers. Here is a question for you, what is the architecture of an ARM processor?
LPC2148 Microcontroller
The LPC2148 microcontroller is designed by Philips (NXP Semiconductor) with several in-built features & peripherals. Due to these reasons, it will make more reliable as well as the efficient option for an application developer. LPC2148 is a 16-bit or 32-bit microcontroller based on ARM7 family.
In power down mode, the oscillator is deactivated and the IC gets no inner clocks. The peripheral registers, processor condition with registers, inner SRAM values are conserved during Power-down mode & the chip logic levels output pins stay fixed.
Because this bus must work accurately at power-up, and the default state at RST (reset) is for the bus to work at 1⁄ 4th of the processor clock rate. The second use of this is to permit power savings whenever an application doesn’t need any peripherals to work at the complete processor rate. Since the VPB-divider is associated with the output of PLL, this remains active throughout an idle mode.
These microcontrollers support two condensed power modes such as power-down mode and idle mode. In Idle mode, instructions execution is balanced until an interrupt or RST occurs. The functions of peripheral maintain operation throughout idle mode & can produce interrupts to cause the CPU to restart finishing. Idle mode removes the power utilized by the CPU, controllers, memory systems, and inner buses.
Each microcontroller from LPC2141/ LPC2142/ LPC2144/ LPC2146/ LPC2148 includes two I2C bus controllers, and this is bidirectional. The inter-IC control can be done with the help of two wires namely an SCL and SDA. Here the SDA & SCL are serial clock line and the serial data line
But, simply a particular master, as well as slave, can converse on the bus throughout a specified data transmit. This microcontroller supports full-duplex transfers, by 4-16 bits data frames used for the flow of data from the master- the slave as well as from the slave-the master.
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In general, a bootloader is a code that executes at the instant the CPU comes out of reset until it passes off control of the system to the OS. It performs basic initialization of the CPU and sometimes some other peripheral devices, such as disk subsystems, sometimes network controllers, perhaps timers, DMA controller, video controller, UART(s), etc. Sometimes it can have an interactive component, or it might be completely invisible.
A Controller Area Network (CAN bus) is a robust vehicle bus standard designed to allow microcontrollers and devices to communicate with each other in applications without a host computer. It is a message-based protocol, designed originally for multiplex electrical wiring within automobiles to save on copper, but can also be used in many other contexts.
The kernel is a computer program that is the core of a computer’s operating system, with complete control over everything in the system. On most systems, it is one of the first programs loaded on start-up (after the bootloader). It handles the rest of the start-up as well as input/output requests from software, translating them into data-processing instructions for the central processing unit. It handles memory and peripherals like keyboards, monitors, printers, and speakers.
Here I have tried to create some collection of “embedded system interview questions with answers” that might ask by your interviewer. These embedded system questions not only for fresher but also good for the experienced person.