# Asic Architecture Interview Questions

## What is an ASIC Engineer?

Application-Specific Integrated Circuits (ASICs) are relatively new to the IT and engineering sector, but are quickly revolutionising the industry because of their specialised nature and potential applications to IoT and machine learning. In terms of the job, ASIC engineers are specialist electronic engineer who works with these custom-built microchips, whether that is designing, testing or building them.

Looking back at the waveform, it would be nice if we could eliminate the second pulse in each set of two pulses on the R pin of the latch (marked as a * on the waveform). This means we just have to use the pulse which occurs during the “00” state of the counter. This is easy enough, since we have to use the “00” from the counter and the “0” from the clock itself – this is just the logic for a 3 input NOR gate!

Most solutions that came in, utilized 4 or 5 flip flops plus a lot more logic than I believe is necessary. The solution, which I believe is minimal requires 3 flops – two working on the rising edge of the clock and generating a count-to-3 counter and an additional flop working on the falling edge of the clock.

A while back, someone sent me the interview question I am about to describe, asking for help. I think it serves a very good example of observing patterns and not rushing into conclusions. I will immediately post the answer after describing the problem. However, I urge you to try and solve it on your own and see what you came up with. On we go with the question…

Allow me to quote from Martin Gardner’s excellent, excellent book Mathematical Carnival (chapter 17): `When a mathematical puzzle is found to contain a major flaw - when the answer is wrong, when there is no answer, or when, contrary to claims, there is more than one answer or a better answer - the puzzle is said to be "cooked". `

Take the clock frequency circuit I posted about here. As I mentioned the XOR gate at the output might cause some duty cycle distortion with some libraries, due to the fact that most XOR gates are not built to be symmetrical with respect to transition delay. Now, assume your library has a perfectly symmetrical NAND gate. Could you modify the circuit so the XOR will be replaced by a NAND gate and still have a clock frequency at the output (You are of course allowed to add more logic on other parts of the circuit).

The above guidance should have provided plenty of advice for businesses interviewing candidates for an ASIC engineering role, but what else do you need to know before conducting an interview? Face to face interviews that involve these kinds of in-depth questions are usually the last stage of the hiring process, so at this point you will have narrowed down your search to a handful of candidates who all show potential for succeeding in the role.

A potential employee’s attitude and personality are often just as important as their skill set, and it is important to take note of how they conduct themselves from arrival right through to leaving the interview. A great piece of advice is to have a member of company staff from a different team or department meet the candidate when they arrive for their interview, and see how they interact and behave whilst not in an official interview setting.

Whilst it is good to follow a predetermined structure in a job interview, be prepared to spend time on certain responses and ask follow-up questions if a candidate mentions anything particularly interesting or unusual. These are the instances where you’ll really get to know a candidate better and determine what it is that makes them stand out.

The responsibility of the final hiring decision will depend on the size of your company, the new hire’s location and whether you have an internal hiring team or manage new employees yourself. It is always worth considering multiple points of view on a candidate before hiring, and considering the impression they made just as much as their skills and experience.