Assertion Based Verification Interview Questions

What is difference between reg, logic & wire datatypes in System Verilog?

Reg – 4 state data type. Reg is a date storage element .It’s not an actual hardware register but it can store values. Register retains their value until next assignment statement. The register variables can be driven or assigned with values inside the procedural blocks like initial or always. Default value of reg variable is “x”.

Wire – 4 state data type. Wire data type is used in the continuous concurrent assignments or port list. It is treated as a wire because it cannot hold or store a value. It can be driven and read. Default value is “z”.

Logic – 4 state data type, similar to reg. The main difference between logic datatype and reg/wire is that a logic can be driven in continuous assignment statement or inside the procedural block. Default value is “x”

Why do we use create method in UVM rather than using new constructor?

We use create () method because, if any overrides are registered with the factory, the create method returns object of override type. So, basically we get child object on parent handle if overrides are registered. Whereas new () method returns object of type its being called on.

With the call for function new, though overrides are registered, the parent object will be created always.

What is virtual class in SystemVerilog?

A virtual class is a class for which instance or object cannot be constructed but you can define the handle to the virtual class. They are used to create code that can be shared across multiple projects

Pure virtual methods can be defined as templates in the virtual class. Basically it forces all extended classes to implement the functions.

Difference between module & class based TB?

Modules instances are created at compile time. They exist from time 0 until the simulation ends. Hence we cannot change the behavior or the TB architecture and cannot be reused.

Class instances can be created and deleted during simulation. Hence we can configure the TB architecture and can be reused.

For Example: Refer to the constraint c_a_b_const in the following code. In the base class, it is defined to always have a value of a< b, but in a derived class, it has been overridden to have always a > b.

A ref keyword is used to pass arguments by reference to a function instead of a value. The subroutine/function shares the reference handle with the caller to access values. This is an efficient way of passing arguments like class objects or arrays of objects where

5) Postponed: There is also a postponed region which is the last phase of current time slot. $monitor, $strobe and other similar events are scheduled for execution in this region. $display events are scheduled for execution in Active and Reactive regions (if called in program blocks).

and initialized just when an entry of the 32K array needs to be referenced. However, associative arrays are also slowest as they internally implement search for elements in the array using a hash.

Soft constraints are generally used to specify default values and distributions for random variables and can be overridden by specialized constraints.

What is the difference between code coverage & functional coverage?

Code coverage measures how much of the code has been executed (statement, branch, expressions in the RTL code).

Why are we using mailboxes to establish the communication between the TB components instead of queues?

Queue is an unpacked array which grows & shrinks automatically. It can be used to model FIFO, LIFO. We can insert & delete the elements from the first, last & in between also.

Mailbox is a higher level concept that is built around a combination of queues and semaphores. If you have only one process reading and writing to the data structure, there is no need to use a mailbox. However if there are more than one thread, a mailbox is a convenient class to use because of blocking methods put & get.

UVM phases are initiated by calling run_test from top module. run_test first creates an instance of test class & initiates all phases sequentially.

Assertion system verilog #sva part1 introduction.

Related Posts

Leave a Reply

Your email address will not be published. Required fields are marked *